1. Technical Field
The present invention is generally directed to address translation for accessing portions of computer memory. More specifically, the present invention is directed to a mechanism for bypassing the translation lookaside buffer (TLB) hierarchy of known address translation systems by providing pre-translated segments for page translations.
2. Description of Related Art
With the advent of faster processors and large amounts of memory in modern computing devices, applications have started using larger working sets, i.e. a larger amount of data and instructions that needs to be loaded into system memory. Faster processors can support a higher level of multi-programming which in turn results in an increase in the cumulative working set size. Despite the huge increase in physical memory in modern computing devices, the size of the memory address mapping mechanisms, e.g. the translation lookaside buffer (TLB), have not increased much due to hardware costs and other constraints.
A translation lookaside buffer (TLB) is a table in the processor that contains cross-references between the virtual and real addresses of recently referenced pages of memory. The TLB functions like a “hot list,” or quick-lookup index, of the pages in main memory that have been most recently accessed.
When a cache miss occurs, data must be fetched from an address in virtual memory. This virtual memory address must be translated into a real-memory address, or physical address. If the real-memory address of a desired page is not in the TLB, a further delay is incurred while the real address is determined by other means.
Because the size of the TLB has not increased with the increase in the size of physical memory, the reach of the TLB in modern computing devices is inadequate for supporting large working sets. As a result, the TLB miss ratio increases as working sets get larger. In addition, large working sets also result in a large page table footprint. This makes it increasingly less likely that the page table entry required to satisfy a TLB miss will be found in the level of cache closest to the processor. Consequently, the amount of time it takes to satisfy TLB misses also increases. TLB misses have become a critical performance bottleneck for large-memory machines.
Proposed solutions to the TLB latency problem include increasing the size of the pages of memory, e.g. superpages, and providing support for multiple page sizes. Superpages are a mechanism that has been devised for reducing the number of translation lookaside buffer (TLB) and page table entries required to map memory. Superpages are large virtual pages used to increase the memory mapped by each page table entry. Superpages increase the relative TLB coverage and reduce the number of TLB misses, which require expensive (slow) address translations.
Superpages are useful when large objects need to be mapped, but are not suitable for all applications. If the application does not require the mapping of large objects, the use of superpages could result in considerable internal fragmentation, without considerably reducing the number of translation entries. Providing additional support for multiple page sizes (including superpages) requires considerable operating system modifications and introduces additional overhead into the translation mechanism.
Thus, it would be beneficial to have an improved mechanism for performing virtual to real address translations that reduces the required size of the page table for large memory systems while minimizing the overhead for performing such translations.